The New Coherence

Efficienct coherence for the next generation of multi/manycore architectures

The VIPS family of cache coherence protocols represents a breakthrough in efficiency and simplicity. VIPS requires negligible area cost and minimal complexity but offers better performance than a full-blown MESI or MOESI protocol at reduced energy consumption (in the on-chip interconnect and memory system). VIPS scales significantly better than other simple protocols (e.g., Token) in terms of network traffic.


VIPS IP is available for licensing.


VIPS Family members

VIPS exits in (compatible) variants depending on the set of features selected, the data classification method employed, and the target architecture. End-to-end VIPS systems can be constructed by combining VIPS variants.

  • VIPS-M: For multicore architectures, VIPS-M eliminates directory indirection, and all invalidations/broadcasts. Seamless virtual cache coherence without extra complexity. Simplicity with power and performance benefits.
  • VIPS-Dir1: A VIPS-M version that classifies data in the on-chip shared cache at a cache-line granularity. A small on-chip classification directory is self-contained (not backed-up) and imposes no restrictions on inclusivity, which is a unique characteristic among any other directory implementation.
  • VIPS-H: Hierarchical version of VIPS-M or VIPS-Dir1 for clustered cache architectures. Out-scales other hierarchical protocols (e.g., H-MOESI or TokenCMP) while still being the simplest (with only a fraction of the number of states of other protocols).
  • VIPS-non-DRF: A VIPS-M version for legacy non-DRF software.
  • VIPS-Callbacks: VIPS-M with hardware support for efficient spin-waiting,
  • ArgoDSM: Software version of VIPS for distributed shared (virtual) memory. Outstanding scalability and performance for large systems. The ArgoDSM system combines VIPS-DSM with a Hierarchical Queue Delegation Locking.